三星单片机S3FB42F解密技术及IC解密实例分析

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   本公司现提供三星(SAMSUNG)系列IC解密——S3FB42F单片机解密实例分析，供广大客户参考借鉴！
   S3FB42F概述
   S3FB42F是一个专为高性能设计的单片CMOS微控制器，使用三星新推出的8位CPU为核心CalmRISC。

　 CalmRISC是一个8位低功耗RISC微处理器。其基本架构如哈佛的风格，也就是说，它具有独立的程序存储器和数据存储器。可以取指令和数据，同时不会造成失速，使用单独的内存访问路径。

    S3FB42F特性

　　·CPU

　　- 8-Bit CalmRISC Core

　　- DSP Architecture (24 x 24-bit MAC)

　　·Memory

　　- Code memory: 144K byte (72K word) half flash type memory

　　- Data memory: 48K byte SRAM + 69K byte flash type memory

　　·STACK

　　- Size: maximum 16 (word)-level.

　　·65 I/O Pins

　　- I/O: 59 pins

　　- Input only: 6 pins

　　·8-Bit Serial I/O Interface

　　- 8-bit transmit/receive or 8-bit receive mode.

　　- LSB first or MSB first transmission selectable.

　　- Internal and external clock source.

　　·8-Bit Basic Timer & Watchdog timer

　　- Programmable basic timer 8-bit counter + WDT 3-bit counter

　　- 8 kinds of clock source

　　- Overflow signal of 8-bit counter makes a basic timer interrupt. And control the oscillation warm-up time

　　- Overflow signal of 3-bit counter makes a system reset.

　　·One 16-Bit Timer/Counter

　　- Programmable interval timer

　　- Two 8-bit timer counter mode and one 16-bit timer counter mode, selectable by S/W

　　·One Real Time Clock

　　- Real time clock generation (0.5 or 1 second)

　　- Buzzer signal generation (1, 2, 4 or 8 kHz)

　　·ROM Code Options

　　- Basic timer counter clock source selecting reset value

　　·I2C, I2S Interface

　　- One-Ch Multi-Master I2C controller

　　- Two-Ch Sony/Phillips I2S controller

　　·UART Interface

　　- One Full-duplex UART controller

　　·USB Specification Compliance (Ver1.0, Ver1.1)

　　- Built in Full Speed Transceiver

　　- Support 1 device address and 4 endpoints.

　　- 1 control endpoint and 3 data endpoints

　　- One 16 bytes endpoint, one 32 bytes end point, and two 64 bytes end points.

　　- Each data endpoint can be configurable as interrupt, bulk and isochronous.

　　·Parallel Port Interface Controller

　　- Interrupt-based operation

　　- Support IEEE Standard 1284 communication mode (compatibility, nibble, byte and ECP mode).

　　- Automatic handshaking mode for any forward or reverse protocol with software enable/disable

　　·SSFDC (Smart MediaTM card) Interface

　　- Control signals are operated by CPU instruction

　　·Random Number Generator

　　- Two ring oscillators

　　- Linear feedback shifter register LFSR8/LFSR16

　　·External Interrupt

　　- 8 source (Edge triggered 6 + Level triggered 2)

　　·ADC

　　- Six 8-bit resolution channels and normal input

　　·Two Power-down Modes

　　- Idle mode: only CPU clock stop.

　　- Stop mode: system clock and CPU clock stop.

　　·Oscillation Sources

　　- Clock synthesizer (Phase-locked loop circuit) based on 32.768 kHz

　　·CPU clock divider circuit(Div by 1, 2, 4, 8, 16, 32, 64, 128)

　　·Instruction Execution Times

　　- 33.3ns at fxx = 30 MHz when 1 cycle instruction

　　- 66.6ns at fxx = 30 MHz when 2 cycle instruction

　　·Operating Temperature

　　- -40 °C to 85 °C

　　·Operating Voltage Range

　　- 3.0 V to 3.6 V at 30 MHz

　　·Package Types

　　- 100-QFP, 100-TQFP

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